Se incluyen a continuación una serie de documentos de interés:
Documentos
[1] Abnous A., Architectural Design and Analysis of a VLIW Processor, M.S. Thesis, University of California, Irvine, 1991 [2] Colwell R.P., Nix R.P., O'Donnell J.J., Papworth D.B., Rodman P.K., A VLIW Architecture for a Trace Scheduling Compiler, IEEE Transactions on Computers, vol. 37, nº 8, págs . 967-979, Agosto 1988 [3] Hennesy J.L., Patterson D.A., Computer Architecture: A Quantitative Approach (3rd edition), Morgan Kaufmann, 2003 [4] Holm J. G., Evaluation Of Some Superscalar And VLIW Processor Designs, M.S. Thesis University of Illinois, 1992 [5] Huck J., Morris D., Ross J., Knies A., Mulder H., Zahir R., Introducing the IA-64 Architecture, IEEE MICRO, Sept-Oct 2000 [6] Yeager K.C., The MIPS R10000 Superscalar Microprocessor, IEEE Micro, vol. 16, nº. 2, págs. 28-40, Abril 1996. [7] Muchnik S. Advanced Compiler Design & Implementation, Morgan Kaufmann, 1997 [8] Patel S.J., Trace Cache Design for Wide-Issue Superscalar Processors, PhD Thesis, The University of Michigan, 1999 [9] Rau B.R., Dynamically Scheduled VLIW Processors, Proc. MICRO-26, IEEE Press, 1993 [10] Shen J., Abraham J. A., Verification of Processor Microarchitectures, En Proc. IEEE VLSI Test Symposium, páginas 189-194, 1999 [11] Sima D., Fountain T., Kacsuk P., Advanced Computer Architectures, A Design Space Approach, Addison-Wesley, 1998 [12] Smith J. E., Sohi G. S., The Microarchitecture of Superscalar Processors, Proc. of the IEEE, Diciembre 1995 [13] Zima H.P., Chapman B.M., Supercompilers for Parallel and Vector Computers, ACM Press Frontier SeriAddison-Wesley, 1990
Otros simuladores
[sim1] Edler J., Hill M., Dinero IV: Trace-Driven Uniprocessor Cache Simulator, Univ. of Wisconsin Computer Sciences [sim2] Lopez P., Calpé R., WinDLXV, Universidad Politécnica de Valencia [sim3] Texas Instruments, Simulador para la familia de procesadores TMS320C6xxx, 2001 [sim4] Wolf M., Wills L., SATSim: A Superscalar Architecture Trace Simulator Using Interactive Animation, Workshop on Computer Architecture Education, Junio 2000